Exemplary embodiments of the present invention generally relate to a semiconductor device and system, and more specifically to a system for synchronizing signals in a semiconductor device.
Semiconductor devices are developed for higher degree of integration and speed. For example, with development of synchronous DRAMs synchronized to a clock, much progress has been made for high-speed operations in the semiconductor devices. Since a synchronous DRAM is generally synchronized to one cycle of an external clock for data input/output, this has presented some limitations to increasing the bandwidth (i.e., the quantity of data inputted/outputted per unit time from a synchronous DRAM) between a synchronous DRAM and a memory controller. Dual data rate (DDR) DRAMs have been developed to further increase the data transfer rate by inputting/outputting the data in synchronization with both the rising and falling edges of a clock.
A DDR DRAM transmits/receives data to/from a memory controller by using a data strobe signal in order to minimize data loss. When a DDR DRAM is transferring data to the memory controller, the DDR DRAM outputs the data in synchronization with a data strobe signal and also outputs the data strobe signal. Then the memory controller receives the data in synchronization with the data strobe signal outputted from the DDR DRAM.
However, since various other devices besides the DDR DRAM and the memory controller are also integrated into the same board in which the DDR DRAM and the memory controller are integrated, the transfer paths of the data strobe signal and the data between the DDR DRAM and the memory controller are not likely to be the same. Because there are differences in the transfer paths, the transfer timings of the data strobe signal and the data are also different from each other. As shown in FIG. 1, for example, the DDR DRAM would output the data strobe signal DQS and the data DQ1, DQ2, DQ3, DQ4 synchronized to the data strobe signal DQS at time t0. However, as shown in FIG. 2, the memory controller cannot synchronize the data DQ1, DQ2, DQ3, DQ4 with the data strobe signal DQS, because the memory controller receives the data strobe signal at the time t1 and the data DQ1, DQ2, DQ3, DQ4 beginning at the time t2.